Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
984
Figure 40-8. DMAC Transfer Flow for Source and Destination Linked List Address
Channel enabled by
software
LLI Fetch
Hardware reprograms
SADDRx, DADDRx, CTRLA/Bx, DSCRx
DMAC buffer transfer
Writeback of HDMA_CTRLAx
register in system memory
Is HDMA in
Row1 of
HDMA State Machine Table?
Channel Disabled by
hardware
Buffer Complete interrupt
generated here
HDMA Transfer Complete
interrupt generated here
yes
no