Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
936
39.7.4 Pen Detect Method
When there is no contact, it is not necessary to perform conversion. However, it is important to detect a contact by
keeping the power consumption as low as possible.
The proposed implementation polarizes the vertical panel by closing the switch on X
P
and ties the horizontal panel
by an embedded resistor connected to Y
M
. This resistor is enabled by a fifth switch. Since there is no contact, no
current is flowing and there is no related power consumption. As soon as a contact occurs, a current is flowing in
the touchscreen and a schmitt trigger detects the voltage in the resistor.
The Touchscreen Interrupt configuration is entered by programming the bit PENDET in the “TSADCC Mode
Register” . If this bit is written at 1, the switch on X
P
and the switch on the resistor are both closed, except when a
touchscreen conversion is in progress.
To complete the circuit, a programmable debouncer is placed at the output of the schmitt trigger. This debouncer is
programmable at 1 ADC Clock period, useful when the system is running at Slow Clock, or at up to 2
15
ADC Clock
periods, but better used to filter noise on the Touchscreen panel when the system is running at high speed. The
debouncer length can be selected by programming the field PENDBC in “TSADCC Mode Register” .
Figure 39-4. Touchscreen Pen Detect
The Touchscreen Pen Detect can be used to generate a TSADCC interrupt to wake up the system or it can be
programmed to trig a conversion, so that a position can be measured as soon as a contact is detected if the
TSADCC is programmed for an operating mode involving the Touchscreen.
The Pen Detect generates two types of status, reported in the “TSADCC Status Register” :
 the bit PENCNT is set as soon as a current flows for a time over the debouncing time as defined by
PENDBC and remains set until TSADCC_SR is read.
 the bit NOCNT is set as soon as no current flows for a time over the debouncing time as defined by
PENDBC and remains set until TSADCC_SR is read.
Both bits are automatically cleared as soon as the Status Register TSADCC_SR is read, and can generate an
interrupt by writing accordingly the “TSADCC Interrupt Enable Register” .
X
P
X
M
Y
M
VDDANA
Y
P
VDDANA
GND
GND
To the ADC
GND
Pen Interrupt
Debouncer
PENDBC