Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
932
By setting the bit LOWRES, the ADC switches in the lowest resolution and the conversion results can be read in
the eight lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding
TSADCC_CDR and of the LDATA field in the TSADCC_LCDR read 0.
Moreover, when a PDC channel is connected to the TSADCC, 10-bit resolution sets the transfer request sizes to
16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers. In this case, the destination buffers
are optimized.
All the conversions for the Touchscreen forces the ADC in 10-bit resolution, regardless of the LOWRES setting.
Further details are given in the section “Operating Modes” on page 939.
39.6.2 ADC Clock
The TSADCC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data
requires Sample and Hold Clock cycles as defined in the field SHTIM of the “TSADCC Mode Register” and 10
ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the “TSADCC Mode Register” .
The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F).
PRESCAL must be programmed in order to provide an ADC clock frequency according to the maximum sampling
rate parameter given in the “Electrical Characteristics” section.
39.6.3 Sleep Mode
The TSADCC Sleep Mode maximizes power saving by automatically deactivating the Analog-to-Digital Converter
cell when it is not being used for conversions. Sleep Mode is enabled by setting the bit SLEEP in “TSADCC Mode
Register” .
The SLEEP of the ADC is automatically managed by the conversion sequencer, which can automatically process
the conversions of all channels at lowest power consumption.
When a trigger occurs, the Analog-to-Digital Converter cell is automatically activated. As the analog cell requires a
start-up time, the logic waits during this time and then starts the conversion on the enabled channels. When all
conversions are complete, the ADC is deactivated until the next trigger.
39.6.4 Startup Time
The Touchscreen ADC has a minimal Startup Time when it exits the Sleep Mode. As the ADC Clock depends on
the application, the user has to program the field STARTUP in the “TSADCC Mode Register” , which defines how
many ADC Clock cycles to wait before performing the first conversion of the sequence.
The field STARTUP can define a Startup Time between 8 and 1024 ADC Clock cycles by steps of 8.
The user must assure that ADC Startup Time given in the section “Electrical Characteristics” is covered by this
wait time.
39.6.5 Sample and Hold Time
In the same way, a minimal Sample and Hold Time is necessary for the TSADCC to guarantee the best converted
final value between selection of two channels. This time depends on the input impedance of the analog input, but
also on the output impedance of the driver providing the signal to the analog input, as there is no input buffer
amplifier.
The Sample and Hold time has to be programmed through the bitfields SHTIM in the “TSADCC Mode Register”
and TSSHTIM in the “TSADCC Touchscreen Register” .
The field SHTIM defines the number of ADC Clock cycles for an analog input, while the field TSSHTIM defines the
number of ADC Clock cycles for a Touchscreen input.
These both fields can define a Sample and Hold time between 1 and 16 ADC Clock cycles.