Datasheet

931
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
39.5 Product Dependencies
39.5.1 Power Management
The TSADC controller is not continuously clocked. The programmer must first enable the TSADC controller Clock
in the Power Management Controller (PMC) before using the TSADC controller. However, if the application does
not require TSADC controller operations, the TSADC controller clock can be stopped when not needed and be
restarted later.
Configuring the TSADC controller does not require the TSADC controller clock to be enabled.
39.5.2 Interrupt Sources
The TSADCC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using
the TSADCC interrupt requires the AIC to be programmed first.
39.5.3 Analog Inputs
The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the TSADCC input is
automatically done as soon as the corresponding channel is enabled by writing the register TSADCC_CHER. By
default, after reset, the PIO lines are configured as input with its pull-up enabled and the TSADCC inputs are
connected to the GND.
39.5.4 I/O Lines
The pin TSADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO
Controller should be set accordingly to assign the pin TSADTRG to the TSADCC function.
39.5.5 Conversion Performances
For performance and electrical characteristics of the TSADCC, see the section “Electrical Characteristics” of the
datasheet.
39.6 Analog-to-digital Converter Functional Description
The TSADCC embeds a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The ADC
supports 8-bit or 10-bit resolutions.
The conversion is performed on a full range between 0V and the reference voltage pin TSADVREF. Analog inputs
between these voltages convert to values based on a linear conversion.
39.6.1 ADC Resolution
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit LOWRES in the
TSADCC Mode Register. See Section 39.11.2 “TSADCC Mode Register” on page 948.
By default, after a reset, the resolution is the highest and the DATA field in the “TSADCC Channel Data Register x
(x = 0..7)” are fully used.
Table 39-2. Peripheral IDs
Instance ID
TSADCC 20
Table 39-3. I/O Lines
Instance Signal I/O Line Peripheral
TSADCC TSADTRG PD28 A