Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
896
38.4.4.5 Example
The first FBD, stored at address 0x00030000, defines the location of the first frame buffer. This address is
programmed in the ISI user interface DMA_P_DSCR. To enable Descriptor fetch operation DMA_P_CTRL register
must be set to 0x00000001. LLI_0 and LLI_1 are the two descriptors of the Linked list.
Destination Address: frame buffer ID0 0x02A000 (LLI_0.DMA_P_ADDR)
Transfer 0 Control Information, fetch and writeback: 0x00000003 (LLI_0.DMA_P_CTRL)
Next FBD address: 0x00030010 (LLI_0.DMA_P_DSCR)
Second FBD, stored at address 0x00030010, defines the location of the second frame buffer.
Destination Address: frame buffer ID1 0x0003A000 (LLI_1.DMA_P_ADDR
Transfer 1 Control information fetch and writeback: 0x00000003 (LLI_1.DMA_P_CTRL)
Next FBD address: 0x00030000, wrapping to first FBD (LLI_1.DMA_P_DSCR)
Using this technique, several frame buffers can be configured through the linked list. Figure 38-6 illustrates a
typical three frame buffer application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1,
frame n+2 is mapped to Frame buffer 2, further frames wrap. A codec request occurs, and the full-size 4:2:2
encoded frame is stored in a dedicated memory space.
Figure 38-6. Three Frame Buffers Application and Memory Mapping
frame n frame n+1 frame n+2frame n-1 frame n+3 frame n+4
Frame Buffer 0
Frame Buffer 1
Frame Buffer 3
4:2:2 Image
Full ROI
ISI config Space
Codec Request
Codec Done
LCD
Memory Space