Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
880
CURRENT_BANK/CONTROL_DIR: Current Bank/Control Direction
Current Bank: (all endpoints except Control endpoint)
These bits are set by hardware to indicate the number of the current bank.
Note: The current bank is updated each time the user:
Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank.
Clears the received OUT data bit to access the next bank.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
Control Direction: (for Control endpoint only)
0: A Control Write is requested by the Host.
1: A Control Read is requested by the Host.
Note1: This bit corresponds with the 7th bit of the bmRequestType (Byte 0 of the Setup Data).
Note2: This bit is updated after receiving new setup data.
BUSY_BANK_STA: Busy Bank Number
These bits are set by hardware to indicate the number of busy banks.
IN endpoint: it indicates the number of busy banks filled by the user, ready for IN transfer.
OUT endpoint: it indicates the number of busy banks filled by OUT transaction from the Host.
BYTE_COUNT: UDPHS Byte Count
Byte count of a received data packet.
This field is incremented after each write into the endpoint (to prepare an IN transfer).
This field is decremented after each reading into the endpoint (OUT transfer).
This field is also updated at RX_BK_RDY flag clear with the next bank.
This field is also updated at TX_PK_RDY flag set with the next bank.
This field is reset by EPT_x of UDPHS_EPTRST register.
SHRT_PCKT: Short Packet
An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register
EPT_Size.
This bit is updated at the same time as the BYTE_COUNT field.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
00 Bank 0 (or single bank)
01 Bank 1
10 Bank 2
11 Invalid
00 All banks are free
01 1 busy bank
10 2 busy banks
11 3 busy banks