Datasheet

845
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
High Bandwidth Isochronous Endpoint OUT
Figure 37-15. Bank Management, Example of Three Transactions per Microframe
USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192 Mb/s (24 MB/s):
3x1024 data bytes per microframe.
To support such a rate, two or three banks may be used to buffer the three consecutive data packets. The
microcontroller (or the DMA) should be able to empty the banks very rapidly (at least 24 MB/s on average).
NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe.
If NB_TRANS > 1 then it is High Bandwidth.
Example:
 If NB_TRANS = 3, the sequence should be either
 MData0
 MData0/Data1
 MData0/Data1/Data2
 If NB_TRANS = 2, the sequence should be either
 MData0
 MData0/Data1
 If NB_TRANS = 1, the sequence should be
 Data0
Isochronous Endpoint Handling: OUT Example
The user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank
with the UDPHS_EPTSTAx register in the three bit fields as follows:
 TOGGLESQ_STA: PID of the data stored in the current bank
 CURRENT_BANK: Number of the bank currently being accessed by the microcontroller.
 BUSY_BANK_STA: Number of busy bank
This is particularly useful in case of a missing data packet.
If the inter-packet delay between the OUT token and the Data is greater than the USB standard, then the ISO-OUT
transaction is ignored. (Payload data is not written, no interrupt is generated to the CPU.)
If there is a data CRC (Cyclic Redundancy Check) error, the payload is, none the less, written in the endpoint. The
ERR_CRISO flag is set in UDPHS_EPTSTAx register.
If the endpoint is already full, the packet is not written in the DPRAM. The ERR_FL_ISO flag is set in
UDPHS_EPTSTAx.
If the payload data is greater than the maximum size of the endpoint, then the ERR_OVFLW flag is set. It is the
task of the CPU to manage this error. The data packet is written in the endpoint (except the extra data).
MDATA 0 MDATA 0 M DATA 1 DATA2DATA 2M DATA 1
t = 0
t = 52.5 µs
(40% of 125 µs)
RX_BK_RDY
t = 125 µs
RX_BK_RDY
USB line
Read Bank 3Read Bank 2Read Bank 1 Read Bank 1
USB bus
Transactions
Microcontroller FIFO
(DPR) Access