Datasheet

837
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
37.5.8.3 Data IN
Bulk IN or Interrupt IN
Data IN packets are sent by the device during the data or the status stage of a control transfer or during an
(interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under the control of the application
or under the control of the DMA channel.
There are three ways for an application to transfer a buffer in several packets over the USB:
 packet by packet (see below)
 64 Kbyte (see below)
 DMA (see below)
Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)
The application can write one or several banks.
A simple algorithm can be used by the application to send packets regardless of the number of banks associated
to the endpoint.
Algorithm Description for Each Packet:
 The application waits for TX_PK_RDY flag to be cleared in the UDPHS_EPTSTAx register before it can
perform a write access to the DPR.
 The application writes one USB packet of data in the DPR through the 64 Kbyte endpoint logical memory
window.
 The application sets TX_PK_RDY flag in the UDPHS_EPTSETSTAx register.
The application is notified that it is possible to write a new packet to the DPR by the TX_PK_RDY interrupt. This
interrupt can be enabled or masked by setting the TX_PK_RDY bit in the
UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register.
Algorithm Description to Fill Several Packets:
Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application
overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must
be set by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register.
The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the intervention of the CPU. This
means that bank validation (set TX_PK_RDY or clear the RX_BK_RDY bit) is done by hardware.
 The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The application must
wait that at least one bank is free.
 The application writes a number of bytes inferior to the number of free DPR banks for the endpoint. Each
time the application writes the last byte of a bank, the TX_PK_RDY signal is automatically set by the
UDPHS.
 If the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set
the TX_PK_RDY bit in the UDPHS_EPTSETSTAx register.
The application is notified that all banks are free, so that it is possible to write another burst of packets by the
BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the
UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers.
This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate.
A Zero Length Packet can be sent by setting just the TX_PKTRDY flag in the UDPHS_EPTSETSTAx register.