Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
834
Configuration examples of UDPHS_EPTCTLx (UDPHS Endpoint Control Register) for Bulk IN endpoint type follow
below.
 With DMA
 AUTO_VALID: Automatically validate the packet and switch to the next bank.
 EPT_ENABL: Enable endpoint.
 Without DMA:
 TX_BK_RDY: An interrupt is generated after each transmission.
 EPT_ENABL: Enable endpoint.
Configuration examples of Bulk OUT endpoint type follow below.
 With DMA
 AUTO_VALID: Automatically validate the packet and switch to the next bank.
 EPT_ENABL: Enable endpoint.
 Without DMA
 RX_BK_RDY: An interrupt is sent after a new packet has been stored in the endpoint FIFO.
 EPT_ENABL: Enable endpoint.
37.5.6 Transfer With DMA
USB packets of any length may be transferred when required by the UDPHS Device. These transfers always
feature sequential addressing.
Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance
boost with paged memories. These clock-cycle consuming memory row (or bank) changes will then likely not
occur, or occur only once instead of dozens times, during a single big USB packet DMA transfer in case another
AHB master addresses the memory. This means up to 128-word single-cycle unbroken AHB bursts for Bulk
endpoints and 256-word single-cycle unbroken bursts for isochronous endpoints. This maximum burst length is
then controlled by the lowest programmed USB endpoint size (EPT_SIZE bit in the UDPHS_EPTCFGx register)
and DMA Size (BUFF_LENGTH bit in the UDPHS_DMACONTROLx register).
The USB 2.0 device average throughput may be up to nearly 60 MBytes. Its internal slave average access latency
decreases as burst length increases due to the 0 wait-state side effect of unchanged endpoints. If at least 0 wait-
state word burst capability is also provided by the external DMA AHB bus slaves, each of both DMA AHB busses
need less than 50% bandwidth allocation for full USB 2.0 bandwidth usage at 30 MHz, and less than 25% at 60
MHz.
The UDPHS DMA Channel Transfer Descriptor is described in “UDPHS DMA Channel Transfer Descriptor” on
page 881.
Note: In case of debug, be careful to address the DMA to an SRAM address even if a remap is done.