Datasheet

823
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of
downstream ports can be determined by the software driver reading the root hub’s operational registers. Device
connection is automatically detected by the USB host port logic.
USB physical transceivers are integrated in the product and driven by the root hub’s ports.
Over current protection on ports can be activated by the USB host controller. Atmel’s standard product does not
dedicate pads to external over current protection.
36.4 Product Dependencies
36.4.1 I/O Lines
HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The embedded USB High
Speed physical transceivers are controlled by the USB host controller.
36.5 I/O Lines
HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The embedded USB High
Speed physical transceivers are controlled by the USB host controller.
One transceiver is shared with USB Device (UDP) High Speed. In this case USB Host High Speed Controller uses
only Port A, ie, the signals HFSDPA, HFSDMA, HHSDPA and HHSDMA.
The port B is driven by the UDP High Speed, the output signals are DFSDP, DFSDM, DHSDP and DHSDM.
The transceiver is automatically selected for Device operation once the UDP High Speed is enabled.
36.5.1 Power Management
The USB Host High Speed requires a 48 MHz clock for the embedded High-speed transceivers. This clock is
provided by the UTMI PLL, it is UPLLCK.
To further reduce power consumption the user can stop UTMI PLL (in this case USB high-speed operations are
not possible). Nevertheless, as the USB OHCI input clock PLLACK can be selected with the USBS bit in the
PMC_USB register, OHCI full-speed operation remains possible.
The High-speed transceiver returns a 30 MHz clock to the USB Host controller.
The user must program the USB OHCI Input Clock and the USBDIV divider in the PMC_USB register to generate
a 48 MHz and a 12 MHz signal with an accuracy of ± 0.25%.
Thus the USB Host peripheral receives three clocks from the Power Management Controller (PMC): the Peripheral
Clock (MCK domain), the UHP48M and the UHP12M (built-in UHP48M divided by four) used by the OHCI to
interface with the bus USB signals (recovered 12 MHz domain) in Full-speed operations.
For High-speed operations, the user has to perform the following:
 Enable UHP peripheral clock in PMC_PCER
 Write PLLCOUNT field in CKGR_UCKR
 Enable UPLL with UPLLEN bit in CKGR_UCKR
 Wait until UTMI_PLL is locked (LOCKU bit in PMC_SR)
 Enable BIAS, with BIASEN bit in CKGR_UCKR
 Select UPLLCK as Input clock of OHCI part (USBS bit in PMC_USB register)
 Program OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV must be 9
(division by 10) if UPLLCK is selected.
 Enable OHCI clocks with UHP bit in PMC_SCER