Datasheet

775
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
35.8.4 Write Operation
In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-
multiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used.
If set, the bit DMAEN in the HSMCI DMA Configuration Register (HSMCI_DMA) enables DMA transfer.
The following flowchart (Figure 35-9) shows how to write a single block with or without use of DMA facilities.
Polling or interrupt method can be used to wait for the end of write according to the contents of the HSMCI
Interrupt Mask Register (HSMCI_IMR).