Datasheet

73
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
11. Reset Controller (RSTC)
11.1 Description
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any
external components. It reports which reset occurred last.
The Reset Controller also drives independently or simultaneously the external reset and the peripheral and
processor resets.
11.2 Embedded Characteristics
The Reset Controller is based on two Power-on Reset cells, one on VDDBU and one on VDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either a general reset
(VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a user reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin. The NRST pin is bidirectional. It
is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external
components or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except
the Backup region. There is no constraint on the length of the reset pulse and the reset controller can guarantee a
minimum pulse length.
The NRST pin integrates a permanent pull-up resistor to VDDIOP0 of about 100 kΩ. NRST is an open drain
output.
The configuration of the Reset Controller is saved as supplied on VDDBU.
11.3 Block Diagram
Figure 11-1. Reset Controller Block Diagram
NRST
Startup
Counter
proc_nreset
wd_fault
periph_nreset
backup_neset
SLCK
Reset
State
Manager
Reset Controller
rstc_irq
NRST
Manager
exter_nreset
nrst_out
Main Supply
POR
WDRPROC
user_reset
Backup Supply
POR