Datasheet

707
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
34.5.1.5 Interrupts
There are 15 interrupt conditions that are detected within the EMAC. These are ORed to make a single interrupt.
Depending on the overall system design, this may be passed through a further level of interrupt collection (interrupt
controller). On receipt of the interrupt signal, the CPU enters the interrupt handler (Refer to the AIC programmer
datasheet). To ascertain which interrupt has been generated, read the interrupt status register. Note that this
register clears itself when read. At reset, all interrupts are disabled. To enable an interrupt, write to interrupt enable
register with the pertinent interrupt bit set to 1. To disable an interrupt, write to interrupt disable register with the
pertinent interrupt bit set to 1. To check whether an interrupt is enabled or disabled, read interrupt mask register: if
the bit is set to 1, the interrupt is disabled.
34.5.1.6 Transmitting Frames
To set up a frame for transmission:
1. Allocate a number (n) of buffers of 128 bytes in system memory.
2. Allocate an area of system memory for transmit data. This does not have to be contiguous, varying byte
lengths can be used as long as they conclude on byte borders.
3. Set-up the transmit buffer list.
4. Set the network control register to enable transmission and enable interrupts.
5. Write data for transmission into these buffers.
6. Write the address to transmit buffer descriptor queue pointer.
7. Write control and length to word one of the transmit buffer descriptor entry.
8. Write to the transmit start bit in the network control register.
34.5.1.7 Receiving Frames
When a frame is received and the receive circuits are enabled, the EMAC checks the address and, in the following
cases, the frame is written to system memory:
 if it matches one of the four specific address registers.
 if it matches the hash address function.
 if it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.
 if the EMAC is configured to copy all frames.
The register receive buffer queue pointer points to the next entry (see Table 34-1 on page 696) and the EMAC
uses this as the address in system memory to write the frame to. Once the frame has been completely and
successfully received and written to system memory, the EMAC then updates the receive buffer descriptor entry
with the reason for the address match and marks the area as being owned by software. Once this is complete an
interrupt receive complete is set. Software is then responsible for handling the data in the buffer and then releasing
the buffer by writing the ownership bit back to 0.
If the EMAC is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is
set. If there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer
not available is set. If the frame is not successfully received, a statistic register is incremented and the frame is
discarded without informing software.