Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
706
Figure 34-2. Receive Buffer List
To create the list of buffers:
1. Allocate a number (n) of buffers of 128 bytes in system memory.
2. Allocate an area 2n words for the receive buffer descriptor entry in system memory and create n entries in
this list. Mark all entries in this list as owned by EMAC, i.e., bit 0 of word 0 set to 0.
3. If less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0 set
to 1).
4. Write address of receive buffer descriptor entry to EMAC register receive_buffer queue pointer.
5. The receive circuits can then be enabled by writing to the address recognition registers and then to the
network control register.
34.5.1.3 Transmit Buffer List
Transmit data is read from areas of data (the buffers) in system memory These buffers are listed in another data
structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of
descriptor entries (as defined in Table 34-2 on page 699) that points to this data structure.
To create this list of buffers:
1. Allocate a number (n) of buffers of 128 bytes in system memory.
2. Allocate an area 2n words for the transmit buffer descriptor entry in system memory and create N entries in
this list. Mark all entries in this list as owned by EMAC, i.e., bit 31 of word 1 set to 0.
3. If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit — bit 30 in word
1 set to 1.
4. Write address of transmit buffer descriptor entry to EMAC register transmit_buffer queue pointer.
5. The transmit circuits can then be enabled by writing to the network control register.
34.5.1.4 Address Matching
The EMAC register-pair hash address and the four specific address register-pairs must be written with the required
values. Each register-pair comprises a bottom register and top register, with the bottom register being written first.
The address matching is disabled for a particular register-pair after the bottom-register has been written and re-
enabled when the top register is written. See “Address Checking Block” on page 701. for details of address
matching. Each register-pair may be written at any time, regardless of whether the receive circuits are enabled or
disabled.
Receive Buffer Queue Pointer
(MAC Register)
Receive Buffer 0
Receive Buffer 1
Receive Buffer N
Receive Buffer Descriptor List
(In memory)
(In memory)