Datasheet

67
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
It uses only one valid code detection: analysis of ARM exception vectors.
The SPI Flash read is done using the Continuous Read command from address 0x0. This command is 0xE8 for
DataFlash and 0x0B for Serial Flash devices.
Supported DataFlash Devices
The SPI Flash Boot program supports the DataFlash devices listed in Table 10-3.
Supported Serial Flash Devices
The SPI Flash Boot program supports all Serial Flash devices.
10.4.3.4 TWI EEPROM Boot
The TWI EEPROM Bootloader uses the TWI0. It uses only one valid code detection. It analyzes the ARM
exception vectors.
Supported TWI EEPROM Devices
TWI EEPROM Boot supports all I
2
C-compatible TWI EEPROM memories using 7 bits device address 0x50.
10.4.4 Hardware and Software Constraints
The NVM drivers use several PIOs in peripheral mode to communicate with devices. Care must be taken when
these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and
electrical conflicts between output pins used by the NVM drivers and the connected devices may occur.
To assure correct functionality, it is recommended to plug in critical devices to other pins not used by NVM.
Table 10-4 on page 68 contains a list of pins that are driven during the boot program execution. These pins are
driven during the boot sequence for a period of less than 1 second if no correct boot program is found.
Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot
program are set to their reset state.
Table 10-3. DataFlash Device
Device Density Page Size (bytes) Number of Pages
AT45DB011 1 Mbit 264 512
AT45DB021 2 Mbits 264 1024
AT45DB041 4 Mbits 264 2048
AT45DB081 8 Mbits 264 4096
AT45DB161 16 Mbits 528 4096
AT45DB321 32 Mbits 528 8192
AT45DB642 64 Mbits 1056 8192