Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
616
Figure 32-50. Slave Node Configuration, NACT = SUBSCRIBE
Figure 32-51. Slave Node Configuration, NACT = IGNORE
32.7.8.15 LIN Frame Handling With the Peripheral DMA Controller
The USART can be used in association with the Peripheral DMA Controller (PDC) in order to transfer data directly
into/from the on- and off-chip memories without any processor intervention.
The PDC uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The PDC always writes in
the Transmit Holding register (US_THR) and it always reads in the Receive Holding register (US_RHR). The size
of the data written or read by the PDC in the USART is always a byte.
Master Node Configuration
The user can choose between two PDC modes by the PDCM bit in the LIN Mode register (US_LINMR):
 PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the PDC in the Transmit
Holding register US_THR (instead of the LIN Mode register US_LINMR). Because the PDC transfer size is
limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS,
CHKDIS, CHKTYP, DLM and FDIS are written. During the second access the 8-bit DLC field is written.
 PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by the user in the
LIN Mode register (US_LINMR).
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response (NACT =
PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT = SUBSCRIBE).
TXRDY
Read
US_RHR
Read
US_LINID
RXRDY
LINIDRX
LINTC
Break Synch Protected
Identifier
Data 1 Data N Checksum
Data 1
Data N-1
Data N-1 Data NData N-2
TXRDY
Read
US_RHR
Read
US_LINID
RXRDY
LINIDRX
LINTC
Break Synch Protected
Identifier
Data 1 Data N ChecksumData N-1