Datasheet

607
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
32.7.8.6 Header Reception (Slave Node Configuration)
All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field,
Synch Field and Identifier Field.
In Slave node configuration, the frame handling starts with the reception of the header.
The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At any time, if 11
consecutive recessive bits are detected on the bus, the USART detects a Break Field. As long as a Break Field
has not been detected, the USART stays idle and the received data are not taken in account.
When a Break Field has been detected, the flag LINBK in the Channel Status register (US_CSR) is set to “1” and
the USART expects the Synch Field character to be 0x55. This field is used to update the actual baud rate in order
to stay synchronized (see Section 32.7.8.7). If the received Synch character is not 0x55, an Inconsistent Synch
Field error is generated (see Section 32.7.8.13).
After receiving the Synch Field, the USART expects to receive the Identifier Field.
When the Identifier Field has been received, the flag LINID in the Channel Status register (US_CSR) is set to “1”.
At this moment the field IDCHR in the LIN Identifier register (US_LINIR) is updated with the received character.
The Identifier parity bits can be automatically computed and checked (see Section 32.7.8.8).The flags LINID and
LINBK are reset by writing the bit RSTSTA at “1” in the Control register (US_CR).
Figure 32-41. Header Reception
32.7.8.7 Slave Node Synchronization
The synchronization is done only in Slave node configuration. The procedure is based on time measurement
between falling edges of the Synch Field. The falling edges are available in distances of 2, 4, 6 and 8 bit times.
Figure 32-42. Synch Field
The time measurement is made by a 19-bit counter clocked by the sampling clock (see Section 32.7.1).
When the start bit of the Synch Field is detected the counter is reset. Then during the next eight t
bit
of the Synch
Field, the counter is incremented. At the end of these eight t
bit
, the counter is stopped. At this moment, the 16 most
RXD
Baud Rate
Clock
Write RSTSTA=1
in US_CR
LINID
US_LINIR
LINBK
Start
Bit
10101010
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7Break Field
13 dominant bits (at 0)
Stop
Bit
Break
Delimiter
1 recessive bit
(at 1)
Synch Byte = 0x55
Start
bit
Stop
bit
Synch Field
8 Tbit
2 Tbit 2 Tbit 2 Tbit 2 Tbit