Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
606
The LIN Mode enables processing LIN frames with a minimum of action from the microprocessor.
32.7.8.1 Modes of operation
The USART can act either as a LIN Master node or as a LIN Slave node.
The node configuration is chosen by setting the USART_MODE field in the USART3 Mode register (US_MR):
 LIN Master Node (USART_MODE = 0xA)
 LIN Slave Node (USART_MODE = 0xB)
In order to avoid unpredicted behavior, any change of the LIN node configuration must be followed by a software
reset of the transmitter and of the receiver (except the initial node configuration after a hardware reset). (See
Section 32.7.8.2)
32.7.8.2 Receiver and Transmitter Control
See “Receiver and Transmitter Control” on page 582.
32.7.8.3 Character Transmission
See “Transmitter Operations” on page 582.
32.7.8.4 Character Reception
See “Receiver Operations” on page 589.
32.7.8.5 Header Transmission (Master Node Configuration)
All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field,
Synch Field and Identifier Field.
So in Master node configuration, the frame handling starts with the sending of the header.
The header is transmitted as soon as the identifier is written in the LIN Identifier register (US_LINIR). At this
moment the flag TXRDY falls.
The Break Field, the Synch Field and the Identifier Field are sent automatically one after the other.
The Break Field consists of 13 dominant bits and 1 recessive bit, the Synch Field is the character 0x55 and the
Identifier corresponds to the character written in the LIN Identifier Register (US_LINIR). The Identifier parity bits
can be automatically computed and sent (see Section 32.7.8.8).
The flag TXRDY rises when the identifier character is transferred into the Shift Register of the transmitter.As soon
as the Synch Break Field is transmitted, the flag LINBK in the Channel Status register (US_CSR) is set to “1”.
Likewise, as soon as the Identifier Field is sent, the flag LINID in the Channel Status register (US_CSR) is set to
“1”. These flags are reset by writing the bit RSTSTA at “1” in the Control register (US_CR).
Figure 32-40. Header Transmission
TXD
Baud Rate
Clock
Start
Bit
Write
US_LINIR
10101010
TXRDY
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7Break Field
13 dominant bits (at 0)
Stop
Bit
Break
Delimiter
1 recessive bit
(at 1)
Synch Byte = 0x55
US_LINIR
ID
LINID
in US_CSR
LINBK
in US_CSR
Write RSTSTA=1
in US_CR