Datasheet

605
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
current character processing is completed, the last character written in US_THR is transferred into the Shift
Register of the transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while
TXRDY is low has no effect and the written character is lost.
If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding Register (US_THR)
is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time.
The UNRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
In SPI Master Mode, the slave select line (NSS) is asserted at low level one t
bit
(t
bit
being the nominal time required
to transmit a bit) before the transmission of the MSB bit and released at high level one t
bit
after the transmission of
the LSB bit. So, the slave select line (NSS) is always released between each character transmission and a
minimum delay of three t
bit
always inserted. However, in order to address slave devices supporting the CSAAT
mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing the
Control Register (US_CR) with the RTSEN bit at 1. The slave select line (NSS) can be released at high level only
by writing the Control Register (US_CR) with the RTSDIS bit at 1 (for example, when all data have been
transferred to the slave device).
In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a
character transmission but only a low level. However, this low level must be present on the slave select line (NSS)
at least one t
bit
before the first serial clock cycle corresponding to the MSB bit.
32.7.7.6 Character Reception
When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the
RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE
(Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The
OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
To ensure correct behavior of the receiver in SPI Slave Mode, the master device sending the frame must ensure a
minimum delay of one t
bit
between each character transmission. The receiver does not require a falling edge of the
slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be
present on the slave select line (NSS) at least one t
bit
before the first serial clock cycle corresponding to the MSB
bit.
32.7.7.7 Receiver Timeout
Because the receiver baud rate clock is active only during data transfers in SPI Mode, a receiver timeout is
impossible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (US_RTOR).
32.7.8 LIN Mode
The LIN Mode provides Master node and Slave node connectivity on a LIN bus.
The LIN (Local Interconnect Network) is a serial communication protocol which efficiently supports the control of
mechatronic nodes in distributed automotive applications.
The main properties of the LIN bus are:
 Single Master/Multiple Slaves concept
 Low cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software,
or as a pure state machine.
 Self synchronization without quartz or ceramic resonator in the slave nodes
 Deterministic signal transmission
 Low cost single-wire implementation
 Speed up to 20 kbit/s
LIN provides cost efficient bus communication where the bandwidth and versatility of CAN are not required.