Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
604
Figure 32-38. SPI Transfer Format (CPHA = 1, 8 bits per transfer)
Figure 32-39. SPI Transfer Format (CPHA = 0, 8 bits per transfer)
32.7.7.4 Receiver and Transmitter Control
See “Receiver and Transmitter Control” on page 582.
32.7.7.5 Character Transmission
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status
bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is
empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the
6
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
SPI Master ->TXD
SPI Slave -> RXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2345 786
MISO
SPI Master ->RXD
SPI Slave -> TXD
SCK
(CPOL = 0)
SCK
(CPOL = 1)
1 2345 7
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
2
2
6