Datasheet

603
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
Operation in SPI Slave Mode is programmed by writing at 0xF the USART_MODE field in the Mode Register. In
this case the SPI lines must be connected as described below:
 The MOSI line drives the input pin RXD
 The MISO line is driven by the output pin TXD
 The SCK line drives the input pin SCK
 The NSS line drives the input pin CTS
In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a software reset of the
transmitter and of the receiver (except the initial configuration after a hardware reset). (See Section 32.7.8.2).
32.7.7.2 Baud Rate
In SPI Mode, the baud rate generator operates in the same way as in USART synchronous mode: See “Baud Rate
in Synchronous Mode or SPI Mode” on page 580. However, there are some restrictions:
In SPI Master Mode:
 The external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set to “1” in the
Mode Register (US_MR), in order to generate correctly the serial clock on the SCK pin.
 To obtain correct behavior of the receiver and the transmitter, the value programmed in CD of must be
superior or equal to 6.
 If the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even to ensure a
50:50 mark/space ratio on the SCK pin, this value can be odd if the internal clock is selected (MCK).
In SPI Slave Mode:
 The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the Mode
Register (US_MR). Likewise, the value written in US_BRGR has no effect, because the clock is provided
directly by the signal on the USART SCK pin.
 To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at
least 4 times lower than the system clock.
32.7.7.3 Data Transfer
Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and
CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). The 9
bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in
SPI Mode (Master or Slave).
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the
CPOL bit in the Mode Register. The clock phase is programmed with the CPHA bit. These two parameters
determine the edges of the clock signal upon which data is driven and sampled. Each of the two parameters has
two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a
master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed
in different configurations, the master must reconfigure itself each time it needs to communicate with a different
slave.
Table 32-14. SPI Bus Protocol Mode
SPI Bus Protocol Mode CPOL CPHA
001
100
211
310