Datasheet

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SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
9.4.2 Test Environment
Figure 9-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example,
the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to
form a single scan chain.
Figure 9-3. Application Test Environment Example
9.5 Debug and Test Pin Description
JTAG
Interface
SAM9G45
Test Adaptor
Chip 2Chip n
Chip 1
ICE/JTAG
Tester
SAM9G45-based Application Board In Test
Table 9-1. Debug and Test Pin List
Pin Name Function Type Active Level
Reset/Test
NRST Microprocessor Reset Input/Output Low
TST Test Mode Select Input High
ICE and JTAG
NTRST Test Reset Signal Input Low
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
RTCK Returned Test Clock Output
JTAGSEL JTAG Selection Input
Debug Unit
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output