Datasheet

519
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
Clock Synchronization in Read Mode
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected.
It is tied low until the shift register is loaded.
Figure 30-28 describes the clock synchronization in Read mode.
Figure 30-28. Clock Synchronization in Read Mode
Notes: 1. TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been
acknowledged or non acknowledged.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
3. SCLWS is automatically set when the clock synchronization mechanism is started.
Clock Synchronization in Write Mode
The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was
not detected, it is tied low until TWI_RHR is read.
Figure 30-29 describes the clock synchronization in Read mode.
DATA1
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
SCLWS
SVACC
SVREAD
TXRDY
TWCK
TWI_THR
TXCOMP
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register
Ack or Nack from the master
DATA0DATA0 DATA2
1
2
1
CLOCK is tied low by the TWI
as long as THR is empty
S
SADR
S
R DATA0A
A
DATA1
A DATA2 NA S
XXXXXXX
2
Write THR
As soon as a START is detected