Datasheet

SAM9G45 [DATASHEET]

Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15

8.9 Bus Interface Unit

The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU

implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between

multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix

and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture.

The multi-master bus architecture has a number of benefits:

 It allows the development of multi-master systems with an increased bus bandwidth and a flexible

architecture.

 Each AHB layer becomes simple because it only has one master, so no arbitration or master-to-slave

muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant,

nor do they have to support retry and split transactions.

 The arbitration becomes effective when more than one master wants to access the same slave

simultaneously.

8.9.1 Supported Transfers

The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight

words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that

the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests.

Table 8-7 gives an overview of the supported transfers and different kinds of transactions they are used for.

8.9.2 Thumb Instruction Fetches

All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the

ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.

8.9.3 Address Alignment

The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary

boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word

boundaries.

Table 8-7. Supported Transfers

HBURST[2:0] Description Operation

Single Single transfer

Single transfer of word, half word, or byte:

 Data write (NCNB, NCB, WT, or WB that has missed in DCache)

 Data read (NCNB or NCB)

 NC instruction fetch (prefetched and non-prefetched)

 Page table walk read

Incr4 Four-word incrementing burst

Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB,

NCB, WT, or WB write.

Incr8 Eight-word incrementing burst Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.

Wrap8 Eight-word wrapping burst Cache linefill