Datasheet

507

SAM9G45 [DATASHEET]

Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15

Figure 30-15. TWI Write Operation with Single Data Byte without Internal Address

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address (DADR)

- Transfer direction bit

Write ==> bit MREAD = 0

Load Transmit register

TWI_THR = Data to send

Read Status register

TXRDY = 1?

Read Status register

TXCOMP = 1?

Transfer finished

Ye s

BEGIN

Write STOP Command

TWI_CR = STOP