Datasheet

465
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
Notes: 1. Reset value of PIO_PSR depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
occurred.
5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second
register.
0x007C–0x009C Reserved
0x00A0 Output Write Enable PIO_OWER Write-only –
0x00A4 Output Write Disable PIO_OWDR Write-only –
0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000
0x00AC Reserved
0x00C0 I/O Delay Register PIO_DELAY0R Read/Write 0x00000000
0x00C4 I/O Delay Register PIO_DELAY1R Read/Write 0x00000000
0x00C8 I/O Delay Register PIO_DELAY2R Read/Write 0x00000000
0x00CC I/O Delay Register PIO_DELAY3R Read/Write 0x00000000
0x00C4–0x00E0 Reserved
0x00E4 Write Protect Mode Register PIO_WPMR Read/Write 0x00000000
0x00E8 Write Protect Status Register PIO_WPSR Read-only 0x00000000
0x00F0–0x00F8 Reserved
Table 29-2. Register Mapping (Continued)
Offset Register Name Access Reset