Datasheet

461
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
Figure 29-6. Input Change Interrupt Timings
29.4.11 Write Protected Registers
To prevent any single software error that may corrupt the PIO behavior, the registers listed below can be write-
protected by setting the WPEN bit in the PIO Write Protect Mode Register (PIO_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the PIO Write Protect Status
Register (PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been
attempted.
The WPVS flag is automatically reset after reading the PIO Write Protect Status Register (PIO_WPSR).
List of the write-protected registers:
 “PIO Enable Register” on page 466
 “PIO Disable Register” on page 467
 “PIO Output Enable Register” on page 469
 “PIO Output Disable Register” on page 470
 “PIO Input Filter Enable Register” on page 472
 “PIO Input Filter Disable Register” on page 473
 “PIO Set Output Data Register” on page 475
 “PIO Clear Output Data Register” on page 476
 “PIO Multi-driver Enable Register” on page 483
 “PIO Multi-driver Disable Register” on page 484
 “PIO Pull Up Disable Register” on page 486
 “PIO Pull Up Enable Register” on page 487
 “PIO Peripheral A Select Register” on page 489
 “PIO Peripheral B Select Register” on page 490
 “PIO Output Write Enable Register” on page 492
 “PIO Output Write Disable Register” on page 493
MCK
Pin Level
Read PIO_ISR
APB Access
PIO_ISR
APB Access