Datasheet

437
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
When operating with decoding, the SPI directly outputs the value defined by the PCS field on NPCS lines of either
the Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing
any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select
defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the
externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make
sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. Figure
28-11 below shows such an implementation.
If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This
is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0.
If the CSAAT bit is used, with or without the DMAC, the Mode Fault detection for NPCS0 line must be disabled.
This is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0.
Figure 28-11. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK
1-of-n Decoder/Demultiplexer
MISO MOSI
NSS
Slave 0
SPCK MISO MOSI
NSS
Slave 1
SPCK MISO MOSI
NSS
Slave 14
NPCS3