Datasheet

435
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
28.7.3.4 Transfer Delays
Figure 28-10 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays
can be programmed to modify the transfer waveforms:
 The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field
in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of
a new one.
 The delay before SPCK, independently programmable for each chip select by writing the field DLYBS.
Allows the start of SPCK to be delayed after the chip select has been asserted.
 The delay between consecutive transfers, independently programmable for each chip select by writing the
DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
Figure 28-10. Programmable Delays
28.7.3.5 Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the
NPCS signals are high before and after each transfer.
 Fixed Peripheral Select: SPI exchanges data with only one peripheral
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the
current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect.
 Variable Peripheral Select: Data can be exchanged with more than one peripheral without having to
reprogram the NPCS field in the SPI_MR register.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the
current peripheral. This means that the peripheral selection can be defined for each new data. The value to write in
the SPI_TDR register as the following format.
[xxxxxxx(7-bit) + LASTXFER(1-bit)
(1)
+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals to the chip
select to assert as defined in Section 28.8.4 (SPI Transmit Data Register) and LASTXFER bit at 0 or 1 depending
on CSAAT bit. CSAAT, LASTXFER and CSNAAT bit are discussed in the Peripheral Deselection in Section
28.7.3.11.
Note: 1. Optional.
28.7.3.6 SPI Peripheral DMA Controller (PDC)
In both fixed and variable mode the Peripheral DMA Controller (PDC) can be used to reduce processor overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal
means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However,
changing the peripheral selection requires the Mode Register to be reprogrammed.
DLYBCS DLYBS DLYBCT DLYBCT
Chip Select 1
Chip Select 2
SPCK