Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
434
Figure 28-9 shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of TX buffer
(ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags behavior within the SPI_SR
(Status Register) during an 8-bit data transfer in fixed mode with the Peripheral Data Controller involved. The PDC
is programmed to transfer and receive three data. The next pointer and counter are not used. The RDRF and
TDRE are not shown because these flags are managed by the PDC when using the PDC.
Figure 28-9. PDC Status Register Flags Behavior
28.7.3.3 Clock Generation
The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK
divided by 255.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable
results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the
Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral
without reprogramming.
MSB LSB654321
SPCK
MOSI
(from master)
NPCS0
MSB LSB654321
12
3
ENDTX
TXEMPTY
MSB LSB654321
MSB LSB654321
MISO
(from slave)
MSB LSB654321 MSB LSB654321
ENDRX
TXBUFE
RXBUFF