Datasheet

427
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
28.6 Product Dependencies
28.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer
must first program the PIO controllers to assign the SPI pins to their peripheral functions.
28.6.2 Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first
configure the PMC to enable the SPI clock.
28.6.3 Interrupt
The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI
interrupt requires programming the AIC before configuring the SPI.
28.6.4 Peripheral DMA Controller (PDC) or Direct Memory Access Controller (DMAC)
The SPI interface can be used in conjunction with the PDC or DMAC in order to reduce processor overhead. For a
full description of the PDC or DMAC, refer to the corresponding section in the full datasheet.
Table 28-2. I/O Lines
Instance Signal I/O Line Peripheral
SPI0 SPI0_MISO PB0 A
SPI0 SPI0_MOSI PB1 A
SPI0 SPI0_NPCS0 PB3 A
SPI0 SPI0_NPCS1 PB18 B
SPI0 SPI0_NPCS1 PD24 A
SPI0 SPI0_NPCS2 PB19 B
SPI0 SPI0_NPCS2 PD25 A
SPI0 SPI0_NPCS3 PD27 B
SPI0 SPI0_SPCK PB2 A
SPI1 SPI1_MISO PB14 A
SPI1 SPI1_MOSI PB15 A
SPI1 SPI1_NPCS0 PB17 A
SPI1 SPI1_NPCS1 PD28 B
SPI1 SPI1_NPCS2 PD18 A
SPI1 SPI1_NPCS3 PD19 A
SPI1 SPI1_SPCK PB16 A
Table 28-3. Peripheral IDs
Instance ID
SPI0 14
SPI1 15