Datasheet

355
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
25.12.7 PMC UTMI Clock Configuration Register
Name: CKGR_UCKR
Address: 0xFFFFFC1C
Access: Read/Write
• UPLLEN: UTMI PLL Enable
0: The UTMI PLL is disabled.
1: The UTMI PLL is enabled.
When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved.
• PLLCOUNT: UTMI PLL Start-up Time
Specifies the number of Slow Clock cycles multiplied by 8 for the UTMI PLL start-up time.
• BIASEN: UTMI BIAS Enable
0: The UTMI BIAS is disabled.
1: The UTMI BIAS is enabled.
• BIASCOUNT: UTMI BIAS Start-up Time
Specifies the number of Slow Clock cycles for the UTMI BIAS start-up time.
31 30 29 28 27 26 25 24
BIASCOUNT – – – BIASEN
23 22 21 20 19 18 17 16
PLLCOUNT – – – UPLLEN
15 14 13 12 11 10 9 8
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