Datasheet

343
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
Code Example:
write_register(CKGR_PLLAR,0x00040805)
If PLLA and divider are enabled, the PLLA input clock is the main clock. PLLA output clock is PLLA input
clock multiplied by 5. Once CKGR_PLLAR has been written, LOCKA bit will be set after eight slow clock
cycles.
3. Setting Bias and High Speed PLL (UPLL) for UTMI
The UTMI PLL is enabled by setting the UPLLEN field in the CKGR_UCKR. The UTMI Bias must is enabled
by setting the BIASEN field in the CKGR_UCKR in the same time. In some cases it may be advantageous to
define a start-up time. This can be achieved by writing a value in the PLLCOUNT field in the CKGR_UCKR.
Once this register has been correctly configured, the user must wait for LOCKU field in the PMC_SR to be
set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the
associated interrupt to LOCKU has been enabled in the PMC_IER.
4. Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the PMC_MCKR.
The CSS field is used to select the clock source of the Master Clock and Processor Clock dividers. By
default, the selected clock source is slow clock.
The PRES field is used to control the Master/Processor Clock prescaler. The user can choose between
different values (1, 2, 4, 8, 16, 32, 64). Prescaler output is the selected clock source divided by PRES
parameter. By default, PRES parameter is set to 1 which means that the input clock of the Master Clock and
Processor Clock dividers is equal to slow clock.
The MDIV field is used to control the Master Clock divider. It is possible to choose between different values
(0, 1, 2, 3). The Master Clock output is Master/Processor Clock Prescaler output divided by 1, 2, 4 or 3,
depending on the value programmed in MDIV.
The PLLADIV2 field is used to control the PLLA Clock divider. It is possible to choose between different
values (0, 1). The PMC PLLA Clock input is divided by 1 or 2, depending on the value programmed in
PLLADIV2.
By default, MDIV and PLLLADIV2 are set to 0, which indicates that Processor Clock is equal to the Master
Clock.
Once the PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR.
This can be done either by polling the status register or by waiting for the interrupt line to be raised if the
associated interrupt to MCKRDY has been enabled in the PMC_IER.
The PMC_MCKR must not be programmed in a single write operation. The preferred programming
sequence for the PMC_MCKR is as follows:
 If a new value for CSS field corresponds to PLLA Clock,
 Program the PRES field in the PMC_MCKR.
 Wait for the MCKRDY bit to be set in the PMC_SR.
 Program the CSS field in the PMC_MCKR.
 Wait for the MCKRDY bit to be set in the PMC_SR.
 If a new value for CSS field corresponds to Main Clock or Slow Clock,
 Program the CSS field in the PMC_MCKR.
 Wait for the MCKRDY bit to be set in the PMC_SR.
 Program the PRES field in the PMC_MCKR.
 Wait for the MCKRDY bit to be set in the PMC_SR.