Datasheet

341
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
Note: The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operation. Refer to the Atmel
application note Optimizing Power Consumption of AT91SAM9261-based Systems, literature number
6217.
When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does
not prevent data transfers from other masters of the system bus.
25.6 USB Device and Host Clocks
The USB Device and Host High Speed ports clocks are controlled by the UDPHS and UHPHS bits in PMC_PCER.
To save power on this peripheral when they are is not used, the user can set these bits in PMC_PCDR. The
UDPHS and UHPHS bits PMC_PCSR gives the activity of these clocks.
The PMC also provides the clocks UHP48M and UHP12M to the USB Host OHCI. The USB Host OHCI clocks are
controlled by the UHP bit in PMC_SCER. To save power on this peripheral when it is not used, the user can set
the UHP bit in PMC_SCDR. The UHP bit in PMC_SCSR gives the activity of this clock. The USB host OHCI
requires both the 12/48 MHz signal and the Master Clock. USBDIV field in PMC_USB register is to be
programmed to 9 (division by 10) for normal operations.
To further reduce power consumption the user can stop UTMI PLL (in this case USB high-speed operations are
not possible). Nevertheless, as the USB OHCI input clock (PLLA or UTMI PLL) can be selected with the USBS bit
in the PMC_USB register, OHCI full-speed operation remains possible.
The user must program the USB OHCI Input Clock and the USBDIV divider in the PMC_USB register to generate
a 48 MHz and a 12 MHz signal with an accuracy of ± 0.25%.
25.7 LPDDR/DDR2 Clock
The Power Management Controller controls the clocks of the DDR memory. It provides SysClk DDR internal clock.
That clock is used by the DDR Controller to provide DDR control, data and DDR clock signals.
The DDR clock can be enabled and disabled with DDRCK bit respectively in PMC_SCER and PMC_SDER
registers. At reset DDR clock is disabled to save power consumption.
The Input clock is the same as Master Clock. The Output SysClk DDR Clock is 2xMCK.
In the case MDIV = ‘00’, PCK = MCK and SysClk DDR and DDRCK clocks are not available.
If Input clock is PLLACK/PLLADIV2, the DDR Controller can drive DDR2 and LPDDR at up to 133 MHz with
MDIV = ‘11’.
To save PLLA power consumption, the user can choose UPLLCK an Input clock for the system. In this case the
DDR Controller can drive LPDDR at up to 120 MHz.
25.8 Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral
Clock Controller. The user can individually enable and disable the Master Clock on the peripherals by writing into
the Peripheral Clock Enable (PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of
the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically
disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its
last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the
system.