Datasheet

339
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
25.3 Block Diagram
Figure 25-1. Power Management Controller Block Diagram
25.3.1 Main Application Modes
The Power Management Controller provides three main application modes.
25.3.1.1 Normal Mode
 PLLA and UPLL are running respectively at 400 MHz and 480 MHz
 USB Device High Speed and Host EHCI High Speed operations are allowed
 Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
 System Input clock is PLLACK, PCK is 400 MHz
 MDIV is ‘11’, MCK is 133 MHz
 DDR2 can be used at up to 133 MHz
25.3.1.2 USB HS and LPDDR Mode
 Only UPLL is running at 480 MHz, PLLA power consumption is saved
 USB Device High Speed and Host EHCI High Speed operations are allowed
 Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
 System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz
 MDIV is ‘01’, MCK is 120 MHz
 Only LPDDR can be used at up to 120 MHz
UHP48M
UHP12M
SysClk DDR
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,.../64
PCK
Processor
Clock
Controller
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
/1 /2 /3 /4
SLCK
MAINCK
Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
pck[..]
ON/OFF
UPLLCK
UPLLCK
USB
OHCI
USBDIV+1
/4
USB
EHCI
USBS
Divider
X /1 /1.5 /2