Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
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25. Power Management Controller (PMC)
25.1 Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user
peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor.
25.2 Embedded Characteristics
The Power Management Controller provides all the clock signals to the system.
PMC input clocks:
 UPLLCK: From UTMI PLL
 PLLACK From PLLA
 SLCK: slow clock from OSC32K or internal RC OSC
 MAINCK: from 12 MHz external oscillator
PMC output clocks
 Processor Clock PCK
 Master Clock MCK, in particular to the Matrix and the memory interfaces. The divider can be 1,2,3 or 4
 DDR system clock equal to 2xMCK
Note: DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK).
 USB Host EHCI High speed clock (UPLLCK)
 USB OHCI clocks (UHP48M and UHP12M)
 Independent peripheral clocks, typically at the frequency of MCK
 Two programmable clock outputs: PCK0 and PCK1
This allows the software control of five flexible operating modes:
 Normal Mode, processor and peripherals running at a programmable frequency
 Idle Mode, processor stopped waiting for an interrupt
 Slow Clock Mode, processor and peripherals running at low frequency
 Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped
waiting for an interrupt
 Backup Mode, Main Power Supplies off, VDDBU powered by a battery