Datasheet

335
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
24.6 Main Oscillator
The Main Oscillator is designed for a 12 MHz fundamental crystal. The 12 MHz is an input of the PLLA and the
UPLL used to generate the 480 MHz USB High Speed Clock (UPLLCK).
Figure 24-4 shows the Main Oscillator block diagram.
Figure 24-4. Main Oscillator Block Diagram
24.6.1 Main Oscillator Connections
The typical crystal connection is illustrated in Figure 24-5. For further details on the electrical characteristics of the
Main Oscillator, see Section 45.2 “DC Characteristics”.
Figure 24-5. Typical Crystal Connection
24.6.2 Main Oscillator Startup Time
The startup time of the 12 MHz Main Oscillator is given in Section 45.2 “DC Characteristics”.
24.6.3 Main Oscillator Control
To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is
selected.
The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCEN
bit in the Main Oscillator Register (CKGR_MOR).
When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit in PMC_SR is
automatically cleared, indicating the main clock is off.
When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to
the startup time of the oscillator. This startup time depends on the crystal frequency connected to the main
oscillator.
When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscillator, the MOSCS
bit in PMC_SR (Status Register) is cleared and the counter starts counting down on the slow clock divided by 8
XIN
XOUT
Main Clock
MAINCK
PLLA and
Divider
PLLA Clock
PLLACK
12M Main
Oscillator
UPLL
UPLLCK
XIN XOUT GNDOSC