Datasheet

331
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
24. Clock Generator
24.1 Description
The Clock Generator User Interface is embedded within the Power Management Controller Interface and is
described in Section 25.12. However, the Clock Generator registers are named CKGR_.
24.2 Embedded Characteristics
The Clock Generator is made up of:
 One Low Power 32768 Hz Slow Clock Oscillator with bypass mode
 One Low-Power RC oscillator
 One 12 MHz Main Oscillator, which can be bypassed
 One 400 to 800 MHz programmable PLLA, capable to provide the clock MCK to the processor and to the
peripherals. This PLL has an input divider to offer a wider range of output frequencies from the 12 MHz
input, the only limitation being the lowest input frequency shall be higher or equal to 2 MHz.
The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL) embedded in the UTMI
macro.
Figure 24-1. Clock Generator Block Diagram
Power
Management
Controller
XIN
XOUT
Main Clock
MAINCK
ControlStatus
PLLA and
Divider
PLLA Clock
PLLACK
12M Main
Oscillator
UPLL
On Chip
RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
Clock Generator
RCEN
UPLLCK
OSCSEL
OSC32EN
OSC32BYP