Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
274
22.3 Functional Description
A page in NAND Flash and SmartMedia memories contains an area for main data and an additional area used for
redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page size corresponds to the number of
words in the main area plus the number of words in the extra area used for redundancy.
Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored
properly over the life of the NAND Flash device, NAND Flash providers recommend to utilize either 1 ECC per 256
bytes of data, 1 ECC per 512 bytes of data or 1 ECC for all of the page.
The only configurations required for ECC are the NAND Flash or the SmartMedia page size (528/2112/4224) and
the type of correction wanted (1 ECC for all the page/1 ECC per 256 bytes of data /1 ECC per 512 bytes of data).
Page size is configured setting the PAGESIZE field in the ECC Mode Register (ECC_MR). Type of correction is
configured setting the TYPECORRECT field in the ECC Mode Register (ECC_MR).
ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND Flash or the
SmartMedia is detected. Read and write access must start at a page boundary.
ECC results are available as soon as the counter reaches the end of the main area. Values in the ECC Parity
Registers (ECC_PR0 to ECC_PR15) are then valid and locked until a new start condition occurs (read/write
command followed by address cycles).
22.3.1 Write Access
Once the Flash memory page is written, the computed ECC codes are available in the ECC Parity (ECC_PR0 to
ECC_PR15) registers. The ECC code values must be written by the software application in the extra area used for
redundancy. The number of write accesses in the extra area is a function of the value of the type of correction field.
For example, for 1 ECC per 256 bytes of data for a page of 512 bytes, only the values of ECC_PR0 and ECC_PR1
must be written by the software application. Other registers are meaningless.
22.3.2 Read Access
After reading the whole data in the main area, the application must perform read accesses to the extra area where
ECC code has been previously stored. Error detection is automatically performed by the ECC controller. Please
note that it is mandatory to read consecutively the entire main area and the locations where Parity and NParity
values have been previously stored to let the ECC controller perform error detection.
The application can check the ECC Status Registers (ECC_SR1/ECC_SR2) for any detected errors. It is up to the
application to correct any detected error. ECC computation can detect four different circumstances:
 No error: XOR between the ECC computation and the ECC code stored at the end of the NAND Flash or
SmartMedia page is equal to 0. No error flags in the ECC Status Registers (ECC_SR1/ECC_SR2).
 Recoverable error: Only the RECERR flags in the ECC Status registers (ECC_SR1/ECC_SR2) are set. The
corrupted word offset in the read page is defined by the WORDADDR field in the ECC Parity Registers
(ECC_PR0 to ECC_PR15). The corrupted bit position in the concerned word is defined in the BITADDR field
in the ECC Parity Registers (ECC_PR0 to ECC_PR15).
 ECC error: The ECCERR flag in the ECC Status Registers (ECC_SR1/ECC_SR2) are set. An error has
been detected in the ECC code stored in the Flash memory. The position of the corrupted bit can be found
by the application performing an XOR between the Parity and the NParity contained in the ECC code stored
in the Flash memory.
 Non correctable error: The MULERR flag in the ECC Status Registers (ECC_SR1/ECC_SR2) are set.
Several unrecoverable errors have been detected in the Flash memory page.
ECC Status Registers, ECC Parity Registers are cleared when a read/write command is detected or a software
reset is performed.