Datasheet

273
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
22. Error Correction Code Controller (ECC)
22.1 Description
NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more invalid bits. Over the
NAND Flash/SmartMedia lifetime, additional invalid blocks may occur which can be detected/corrected by ECC
code.
The ECC Controller is a mechanism that encodes data in a manner that makes possible the identification and
correction of certain errors in data. The ECC controller is capable of single bit error correction and 2-bit random
detection. When NAND Flash/SmartMedia have more than 2 bits of errors, the data cannot be corrected.
The ECC user interface is compliant with the ARM Advanced Peripheral Bus (APB rev2).
22.2 Block Diagram
Figure 22-1. Block Diagram
User Interface
Ctrl/ECC Algorithm
Static
Memory
Controller
APB
NAND Flash
SmartMedia
Logic
ECC
Controller