Datasheet

269
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
21.8.10 DDRSDRC High Speed Register
Name: DDRSDRC_HS
Address: 0xFFFFE62C (0), 0xFFFFE42C (1)
Access: Read/Write
This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271.
• DIS_ANTICIP_READ: Anticip Read Access
0: Anticip read access is enabled.
1: Anticip read access is disabled (default).
DIS_ANTICIP_READ allows DDR2 read access optimization with multi-port.
As this feature is based on the “bank open policy”, the software must map different buffers in different DDR2 banks to take
advantage of that feature.
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DIS_ANTICIP_
READ
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