Datasheet

263
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
21.8.5 DDRSDRC Timing Parameter 1 Register
Name: DDRSDRC_TPR1
Address: 0xFFFFE610 (0), 0xFFFFE410 (1)
Access: Read/Write
This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271.
• TRFC: Row Cycle Delay
Reset value is 8 cycles.
This field defines the delay between a Refresh and an Activate command or Refresh command in number of cycles. Num-
ber of cycles is between 0 and 31
• TXSNR: Exit Self Refresh Delay to Non-read Command
Reset value is 8 cycles.
This field defines the delay between CKE set high and a non Read Command in number of cycles. Number of cycles is
between 0 and 255. This field is used for SDR-SDRAM and DDR-SDRAM devices. In the case of SDR-SDRAM devices
and Low-power DDR1-SDRAM, this field is equivalent to TXSR timing.
• TXSRD: ExiT Self Refresh Delay to Read Command
Reset value is 200 cycles.
This field defines the delay between CKE set high and a Read Command in number of cycles. Number of cycles is
between 0 and 255 cycles. This field is unique to DDR-SDRAM devices. In the case of a Low-power DDR1-SDRAM, this
field must be written to 0.
• TXP: Exit Power-down Delay to First Command
Reset value is 3 cycles.
This field defines the delay between CKE set high and a Valid Command in number of cycles. Number of cycles is between
0 and 15 cycles. This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices.
31 30 29 28 27 26 25 24
–––– TXP
23 22 21 20 19 18 17 16
TXSRD
15 14 13 12 11 10 9 8
TXSNR
76543210
––– TRFC