Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
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• TWTR: Internal Write to Read Delay
Reset value is 0.
This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices.
This field defines the internal write to read command Time in number of cycles. Number of cycles is between 1 and 7.
In the case of low-power DDR1-SDRAM device the coding is different:
• REDUCE_WRRD: Reduce Write to Read Delay
Reset value is 0.
This field reduces the delay between write to read access for low-power DDR-SDRAM devices with a latency equal to 2.
To use this feature, TWTR field must be equal to 0. Important to note is that some devices do not support this feature.
• TMRD: Load Mode Register Command to Active or Refresh Command
Reset value is 2 cycles.
This field defines the delay between a Load mode register command and an active or refresh command in number of
cycles. Number of cycles is between 0 and 15.
Value Name Description
1 ONE does 1
2 TWO does 2
3 THREE does 3
4 FOUR does 4
5 FIVE does 5
6 SIX does 6
7 SEVEN does 7
Value Name Description
0 ONE does 1
1 TWO does 2
2–7 – Reserved