Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
258
21.8.3 DDRSDRC Configuration Register
Name: DDRSDRC_CR
Address: 0xFFFFE608 (0), 0xFFFFE408 (1)
Access: Read/Write
This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271.
• NC: Number of Column Bits
Reset value is 9 column bits.
SDR-SDRAM devices with eight columns in 16-bit mode are not supported.
• NR: Number of Row Bits
Reset value is 12 row bits.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––ACTBST–EBISHARE
15 14 13 12 11 10 9 8
– OCD – – DIS_DLL DIC/DS
76543210
DLL CAS NR NC
NC DDR - Column bits SDR - Column bits
00 9 8
01 10 9
10 11 10
11 12 11
NR Row bits
00 11
01 12
10 13
11 14