Datasheet

257
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
21.8.2 DDRSDRC Refresh Timer Register
Name: DDRSDRC_RTR
Address: 0xFFFFE604 (0), 0xFFFFE404 (1)
Access: Read/Write
This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 271.
• COUNT: DDRSDRC Refresh Timer Count
This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a
refresh sequence is initiated.
SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the DDRSDRC clock fre-
quency (MCK: Master Clock) and the number of rows in the device.
For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of Refresh Timer Count bit is pro-
grammed: (((64 x 10
-3
)/8192) x100 x10
6
= 781 or 0x030D.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
–––– COUNT
76543210
COUNT