Datasheet

251
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
21.5.6 Write Protected Registers
To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed below can be write-
protected by setting the WPEN bit in the DDRSDRC Write Protect Mode Register (DDRSDRC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC Write Protect
Status Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in which register the write access has
been attempted.
The WPVS flag is automatically reset after reading the DDRSDRC Write Protect Status Register
(DDRSDRC_WPSR).
Following is a list of the write protected registers:
 “DDRSDRC Mode Register” on page 256
 “DDRSDRC Refresh Timer Register” on page 257
 “DDRSDRC Configuration Register” on page 258
 “DDRSDRC Timing Parameter 0 Register” on page 261
 “DDRSDRC Timing Parameter 1 Register” on page 263
 “DDRSDRC Timing Parameter 2 Register” on page 264
 “DDRSDRC Memory Device Register” on page 267
 “DDRSDRC High Speed Register” on page 269