Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
248
21.5.4.3 Deep Power-down Mode
The deep power-down mode is a new feature of the Low-power SDRAM. When this mode is activated, all internal
voltage generators inside the device are stopped and all data is lost.
This mode is activated by setting the low-power command bits [LPCB] to ‘11’. When this mode is enabled, the
DDRSDRC leaves normal mode (DDRSDRC_MR.MODE = 000) and the controller is frozen. To exit deep power-
down mode, the low-power bits (LPCB) must be set to “00”, an initialization sequence must be generated by
software. See Section 21.4.2 “Low-power DDR1-SDRAM Initialization” on page 231.
Figure 21-23. Deep Power-down Mode Entry
21.5.4.4 Reset Mode
The reset mode is a feature of the DDR2-SDRAM. This mode is activated by setting the low-power command bits
(LPCB) to 11 and the clock frozen command bit (CLK_FR) to 1.
When this mode is enabled, the DDRSDRC leaves normal mode (DDRSDRC_MR.MODE = 000) and the
controller is frozen. Before enabling this mode, the end user must assume there is not an access in progress.
To exit reset mode, the low-power command bits (LPCB) must be set to “00”, clock frozen command bit (CLK_FR)
set to 0 and an initialization sequence must be generated by software. See Section 21.4.3 “DDR2-SDRAM
Initialization” on page 232.
NOP READ BST NOP PRCHG NOP DEEPOWER NOP
0
Trp
Enter Deep
Power-down
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[1:0]
Da Db
D[15:0]
3
DM[1:0]