Datasheet

247
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
21.5.4.2 Power-down Mode
This mode is activated by setting the low-power command bits [LPCB] to ‘10’.
Power-down mode is used when no access to the SDRAM device is possible. In this mode, power consumption is
greater than in self refresh mode. This state is similar to normal mode (No low-power mode/No self refresh mode),
but the CKE pin is low and the input and output buffers are deactivated as soon the SDRAM device is no longer
accessible. In contrast to self refresh mode, the SDRAM device cannot remain in low-power mode longer than the
refresh period (64 ms). As no auto-refresh operations are performed in this mode, the DDRSDRC carries out the
refresh operation. In order to exit low-power mode, a NOP command is required in the case of Low-power SDR-
SDRAM and SDR-SDRAM devices. In the case of Low-power DDR1-SDRAM devices, the controller generates a
NOP command during a delay of at least TXP. In addition, Low-power DDR1-SDRAM and DDR2-SDRAM must
remain in power-down mode for a minimum period of TCKE periods.
The exit procedure is faster than in self refresh mode. See Figure 21-22. The DDRSDRC returns to power-down
mode as soon as the SDRAM device is not selected. It is possible to define when power-down mode is enabled by
setting the register LPR, timeout command bit.
 00 = Power-down mode is enabled as soon as the SDRAM device is not selected
 01 = Power-down mode is enabled 64 clock cycles after completion of the last access
 10 = Power-down mode is enabled 128 clock cycles after completion of the last access
Figure 21-22. Power-down Entry/Exit, Timeout = 0
Entry power down mode
Exit power down mode
SDCLK
A[12:0]
READ BST NOP READ
COMMAND
CKE
0
BA[1:0]
DQS[1:0]
Da Db
D[15:0]
3
DM[1:0]