Datasheet

245
SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
Figure 21-18. Self Refresh Mode Entry, Timeout = 1 or 2
Figure 21-19. Self Refresh Mode Exit
NOP READ BST NOP
0
Da Db
64 or 128
wait states
3
PRCHG NOP ARFSH NOP
Trp
Enter Self refresh
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[1:0]
D[15:0]
DM[1:0]
NOP VALID NOP
0
TXNRD/TXSRD (DDR device)
TXSR (Low-power DDR1 device)
TXSR (Low-power SDR, SDR-SDRAM device)
Exit Self Refresh mode
clock must be stable
before exiting self refresh mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[1:0]
DaDb
D[15:0]
3
DM[1:0]