Datasheet

SAM9G45 [DATASHEET]
Atmel-6438O-ATARM-SAM9G45-Datasheet_08-Dec-15
244
parameters and Drive Strength (DS). These parameters are set during the initialization phase. After initialization,
as soon as PASR/DS/TCSR fields are modified, the Extended Mode Register in the memory of the external device
is accessed automatically and PASR/DS/TCSR bits are updated before entry into self refresh mode if DDRSDRC
does not share an external bus with another controller or during a refresh command, and a pending read or write
access, if DDRSDRC does share an external bus with another controller. This type of update depends on the
value of the UPD_MR field (see Section 21.8.7 “DDRSDRC Low-power Register” on page 265).
The low-power SDR-SDRAM must remain in self refresh mode for a minimum period of TRAS periods and may
remain in self refresh mode for an indefinite period. (See Figure 21-17)
The low-power DDR1-SDRAM must remain in self refresh mode for a minimum of TRFC periods and may remain
in self refresh mode for an indefinite period.
The DDR2-SDRAM must remain in self refresh mode for a minimum of TCKE periods and may remain in self
refresh mode for an indefinite period.
Figure 21-17. Self Refresh Mode Entry, Timeout = 0
NOP READ BST NOP PRCHG NOP ARFSH NOP
0
Trp
Enter Self refresh
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[0:1]
Da Db
D[15:0]
3
DM[1:0]